In modern high frequency integrated circuits, it is often necessary to generate internal clocks at different frequencies from a reference clock. Conventionally, a Phase-Locked Loop (PLL) or a Delay-Locked Loop (DLL) has been used to generate a clock at the different frequency.
Devices in a computer, such as a CPU, a memory and a video card, normally operate at a standard frequency. However, in order to achieve higher performance, many consumers “overclock” the normal operating frequency of these devices, making them operate faster due to the higher clock frequency. This overclocking can cause a number of problems. Some of these problems may be improper function of the device because it cannot operate properly at the higher frequency and overheating of the device.
Another problem is stability of a PLL responding to the change in the clock frequency. To enhance PLL stability, a frequency ramp ratio and frequency spike during overclocking should be limited to some extent in order to keep the system working normally. Common rules of thumb are to maintain the frequency ramp to 1 MHz/microsecond or less and to maintain frequency spikes to 1 MHz or less.
A common way to meet these overclock requirements is to employ a small bandwidth for the PLL while overclocking and a normal larger bandwidth for the PLL after overclocking. The small bandwidth allows the PLL to track a frequency change in a relatively long time, meeting the frequency ramp ratio requirement. However, large changes in the bandwidth of a PLL can cause large frequency spikes, which may fail the frequency spike requirements.
There is a need for an improved PLL that can respond to these reference clock frequency changes while staying stable and not causing the device with the PLL to malfunction due to the PLL adapting to the new frequency.